With increasing demands for higher electronic performances and miniaturization, multichip module arrangement has become a trend. Multichip module is an apparatus having at least 2 chips adhered onto a single chip carrier such as a substrate or a leadframe. The chip-to-chip carrier bonding manner can be generally categorized into two: One method is by spacing chips next to each other on a chip carrier. This bonding method essentially would not increase the overall height of the semiconductor package, but the chip carrier must contain a large area of die attachment area as to accommodate the required chip numbers. This increased chip carrier surface will generate a higher thermal stress, and therefore resulting in a warpage of the chip carrier and subsequently an occurrence of delamination at the interface between the chip and the chip carrier, making this method facing much more reliability concerns. The other method is by adhering chips in a perpendicularly stacked manner. Although this method would increase the overall height of the semiconductor package, it is widely used by most semiconductor manufacturers because this method avoids the chip carrier to be oversized and therefore eliminates the occurrence of warpage or delamination.
A stacked multichip module is commonly structured as shown in FIG. 8, in which the stacked multichip module 6 has a first chip 61 adhered to a substrate 60, a second chip 64 adhered to the first chip 61, and electrically connecting the first chip 61 and the second chip 64 to the substrate 60 via first gold wires 62 and second gold wires 65 respectively. In addition, the second chip 64 has to be smaller in size than that of the first chip 61, as to avoid the second chip 64 making any contact or impeding the bonding between the first gold wires 62 and the first chip 61. In such a case, the top-most chip would have the smallest size, that is, the surface for disposing electronic circuits and electronic elements is reduced, which is disadvantageous for developing high-density integrated circuits.
In order to avoid the foregoing semiconductor package being restricted to the size and not able to achieve high density integration, U.S. Pat. No. 5,323,060 entitled “Multichip Module Having A Stacked Chip Arrangement” and U.S. Pat. No. 6,005,778 entitled “Chip Stacking and Capacitor Mounting Arrangement Including Spacers” discloses a semiconductor package having an outermost chip extending outwardly to solve this problem. As shown in FIG. 9, the semiconductor package 6 is provided as follows: a first chip 61 being adhered and electrically connected to the substrate 60 via first bonding wires 62; adhering an insulator apparatus 63 of predetermined thickness to the active surface 610 of the first chip 61 whereon bonding pads are not disposed. The insulator apparatus 63 can be an insulated tape, a dummy die that do not perform electrical factions or using a silicon member, however the height H of the insulator apparatus 63 must be larger than the loop height of the first bonding wires 62, which is defined by the maximum distance between the active surface 610 of the first chip 61 and the vertexes of the outwardly projecting loops of the bonding wires, so as to avoid the second chip 64 in contact with the first bonding wires 62 when placing onto the insulator apparatus 63, which would otherwise cause shortage.
The insulator apparatus 63 provides clearance larger than the loop height of the first bonding wires 62 between the bottommost chip and the superimposed topmost chip, so as to prevent the second chip 64 making contact with the first bonding wires even extending outwardly atop of the bonding loop and eliminate shortage from occurrence. In this case, the size of the second chip 64 is not necessary be restricted and the size larger than the first chip 61 is also applicable to use, therefore largely improving the capability of forming integrated circuits with higher density.
However, when using insulated tapes made by adhesive materials such as polyimide for adhering the second chip 64, because of the high fluidity the planarity of the second chip 64 is difficult to achieve. Moreover, because of the Coefficient of Thermal Expansion (CTE) differences between the adhesive materials and the chip is great, during temperature cycles of the latter procedures the chip bonding surface may be easily suffered from warpage, delamination or even chip cracking. Thus, as to solve this problem, the manufacturers developed a so-called dummy die, which does not perform electrical functions, or a stacked semiconductor package having an insulator apparatus made by silicon, the same materials as the chip. The manufacturing steps of this package are illustrated as follows: firstly, preparing a chip carrier 60 whereon a first chip is adhered, and applying a first adhesive layer 613 on the active surface 610 of the first chip 61; then after adhering and curing an insulator apparatus 63 of a predetermined height to the first adhesive layer 613, a wire bonding process is carried out to electrically connect the first chip 61 to the chip carrier 60; following that, a second chip 64 is adhered to the insulator apparatus 63 via the second adhesive layer 614 applied previously on the insulator apparatus 63, and after curing and wire bonding process the second chip 64 is also electrically connected to the chip carrier 60 to form a multi-chip stacked semiconductor package 6.
The foregoing method although can successfully overcome the problem of differences in CTE between the chip and the insulator apparatus, this method is costly and the manufacturing procedures is complex and prolonged, making the final yield difficult to enhanced. Moreover, as adhesives of high fluidity is required to be applied over the active surface of the first chip or the surface of the insulator apparatus prior to bonding between the insulator apparatus and the topmost chip (i.e. the second chip), it is common that the adhesives would lead to the deviation of the insulator or the topmost chip or even damage the first chip pads. As such, the functionality and chip bonding reliability concerns for the packaged product still exist.
In order to solve the foregoing problem, U.S. Pat. No. 6,388,313 discloses a stacked multichip semiconductor packaging method in which a portion of a first bonding wires is directly embedded into an adhesive, so as to prevent the second chip placed on the adhesive from contacting with gold wires. As shown in FIG. 11, this method is substantially very similar to the foregoing method using an adhesive as an insulator apparatus. Firstly, forming a plurality of studs on the active surface 610 of a first chip 61 at positions opposing to the bonding pads and using reverse bonding techniques to bond the other ends of the first bonding wires 62 where one end is adhered to a chip carrier, to the corresponding stud points. Then using print screening methods to apply an adhesive 63 on the active surface 610 of the first chip 61 until a desired thickness is achieved allowing the first bonding wires 62 positioned above the first chip 61, to be completely embedded inside the adhesive 63. It is then followed by pressing the second chip 64 against the adhesive layer 63 and then the chip stacking method is accomplished.
This packaging method utilizes reverse bonding technique to reduce the loop height to about 2 mils, and then applying an adhesive to encapsulate parts of the wire loops. As the adhesive layer is thickened only a little to avoid the second chip from contacting with gold wires, the overall height of the packaged product can be greatly reduced. However, one drawback is that for to the above-mentioned reverse bonding technique, the formation of a plurality of studs on the first chip for wire bonding is required prior to reverse bonding, making the procedures longer and costly. In addition, as the Coefficient of Thermal Expansion (CTE) between the adhesive and the gold wires is great, the gold wires embedded in the adhesive may be easily broken due to different thermal stress under thermal cycles at latter procedures and as a result, the electronic performances of gold wires may be seriously impaired. Besides, during bonding of the second chip, a highly accurate control equipment must be additionally incorporated to accurately control the bond force of the second chip against the adhesive layer, which further increases the overall manufacturing cost.